The present invention relates to a driving circuit for a plasma display panel, and more particularly, to a cathode driving circuit for a plasma display panel.
FIG. 1 shows the structure of a conventional direct current memory type plasma display panel (PDP).
In FIG. 1, the PDP has a front plate 1, a rear plate 2, a plurality of anodes 3 arranged in a stripe form crosswise on the front plate 1, a trigger electrode 4 installed on the whole surface of the rear plate 2, a dielectric 5 covering the whole surface of the trigger electrode 4, a barrier 6 formed in a shape of lattice on the dielectric 5, a plurality of stripe-shaped sustaining anodes 7 formed in one side of the barrier 6 and a plurality of stripe-shaped cathodes 8 formed in the other side of the barrier 6.
FIGS. 2A through 2D show waveforms for driving the conventional direct current memory type PDP. FIG. 2A shows the pulse applied to a data electrode, FIG. 2B shows the pulse applied to the sustaining anode, FIG. 2C shows the pulse applied to the trigger electrode and FIG. 2D shows the pulse applied to the cathode.
The method for driving the PDP as shown in FIG. 1 is hereinafter described using the above mentioned waveforms. The operation of the PDP includes the steps of trigger setting, trigger discharging, primary discharging, sustaining and erasing. The operation of each step is described as follows.
If a trigger voltage -VT (FIG. 2C) is applied to the trigger electrode 4 and a voltage VW (FIG. 2A) is applied to the data electrode, the trigger setting occurs to accumulate positive charges on the dielectric 5.
The trigger discharging happens when a voltage -VK (FIG. 2D) is applied to a first cathode to discharge the positive charges accumulated on the dielectric 5 around the first cathode.
The primary discharging step is performed if a voltage -VK is applied to the first cathode and data applied to anode 3 exists.
The discharge generated in the primary discharging step is sustained if a voltage VSA (FIG. 2B) is applied to the sustaining anode 7 and a voltage -VSK (FIG. 2D) is applied to cathode 8.
The discharge is eliminated when a voltage -VB (FIG. 2D) is applied to the cathodes 8.
If the voltage difference applied between two electrodes is greater than a discharge starting voltage, discharging is started. If the voltage difference applied between two electrodes is greater than a discharge sustaining voltage, discharging is sustained. If the voltage difference applied between two electrodes is lower than a discharge sustaining voltage, discharging is eliminated.
In order to operate as described above, the circuits for generating the pulses applied to the respective electrodes as shown in FIGS. 2A through 2D are necessary. Among them, the configuration of the circuit for driving cathodes is described.
FIG. 3 is a cathode driving circuit diagram of a conventional PDP.
In FIG. 3, the circuit includes first through fourth shift registers 10, 20, 30 and 40 for storing and outputting four corresponding data signals D1, D2, D3 and D4 in accordance with four clock signals CK1, CK2, CK3 and CK4, respectively, AND gates 50, 60, 70 and 80 for performing AND-operations by inputting the output signals of the shift registers 10, 20, 30 and 40 and four corresponding enabling signals EN1, EN2, EN3 and EN4, respectively, a PMOS transistor Q1 having a gate electrode which inputs the output signal of the AND gate 50 and a source electrode to which a voltage -VB is applied, a diode 90 having a cathode electrode connected to the source electrode of the PMOS transistor Q1 and an anode electrode connected to the drain electrode of the PMOS transistor Q1, a diode 130 having a cathode electrode connected to a drain electrode of the PMOS transistor Q1 and an anode electrode connected to an output terminal Kn, a NMOS transistor Q2 having a gate electrode which inputs the output signal of the AND gate 60, a drain electrode connected to the cathode electrode of the diode 130 and a source electrode to which a voltage -VSK is applied, a diode 100 having a cathode electrode connected to the source electrode of the NMOS transistor Q2 and an anode electrode connected to the drain electrode of the NMOS transistor Q2, NMOS transistors Q3 and Q4 having gate electrodes which input the output signals of the AND gates 70 and 80, drain electrodes connected to the drain electrode of the PMOS transistor Q1 and source electrodes to which a voltage -VK is applied, respectively, a diode 110 having a cathode electrode connected to the source electrode of the NMOS transistor Q3 and an anode electrode connected to the drain electrode of the NMOS transistor Q3, and a diode 120 having a cathode electrode connected to the source electrode of the NMOS transistor Q4 and an anode electrode connected to the drain electrode of the NMOS transistor Q4.
FIG. 4 shows the operation of the circuit shown in FIG. 3 and a waveform generated through the output terminal Kn.
The operation of the cathode driving circuit is described as follows with reference to FIGS. 3 and 4.
During a first period (1), the waveform in case the NMOS transistor Q4 is on and the PMOS transistor Q1 and the NMOS transistors Q2 and Q3 are off, is shown and a voltage -VK is generated.
During a second period (2), the waveform in case the PMOS transistor Q1 is on and the NMOS transistors Q2, Q3 and Q4 are off, is shown and a voltage -VB is generated.
During a third period (3), the waveform in case the NMOS transistor Q3 is on and the PMOS transistor Q1 and the NMOS transistors Q2 and Q4 are off, is shown and a voltage -VK is generated.
During a fourth period (4), the waveform in case the NMOS transistor Q2 is on and the PMOS transistor Q1, the NMOS transisters Q3 and Q4 are off, is shown and a voltage -VSK is generated.
However, since the configuration of the conventional cathode driving circuit is complicated, the chip space for its integration occupies much.